Dynamic random access memory (DRAM) devices are frequently used in memory applications requiring high capacity storage and high data bandwidth during write and read operations. A conventional DRAM device includes a bank of memory cells arranged as a plurality of rows and columns of memory cells that are connected to word lines and bit lines, respectively. Each memory cell may be configured to include an access transistor and a storage capacitor configured to retain binary data (“1” or “0”) therein as stored charge. The access transistor typically includes a gate electrode, which is connected to a respective word line, a source terminal, which is electrically connected to a respective bit line and a drain terminal, which is electrically connected to an electrode (e.g., lower electrode) of the storage capacitor.
Unfortunately, the data stored within a storage capacitor of a DRAM cell is treated as “volatile” data that may, as a result of charge leakage from the storage capacitor, degrade even when power to the DRAM device is not interrupted. In order to prevent this degradation of data from causing data errors, the data in each memory cell of a DRAM device is periodically “refreshed.” Accordingly, if a DRAM cell is storing a data “1” value as stored charge within a respective storage capacitor, then a data “1” value may be periodically read from the cell and then immediately rewritten back into the cell at full value in order to replenish the charge in the storage capacitor. This replenishment of charge in the storage capacitor operates as a “refresh” of the data retained by the DRAM cell. However, in the event the frequency at which a bank of DRAM cells is refreshed becomes too high, then the performance of the DRAM device may suffer and thereby limit the number of write and read operations that may be performed within the DRAM.
FIG. 1 is a graph illustrating two curves G11 and G13 as a function of DRAM device temperature (° C.). The first curve G11, which is associated with a vertical axis on the right side of the graph, illustrates the value of storage capacitor leakage current (ICC6) within a core of a DRAM device as a function of DRAM device temperature. As illustrated by G11, the storage capacitor leakage current increases from 25 uA to 900 uA as a function of temperature in a range between 6° C. and 125° C. The second curve G13, which is associated with a vertical axis on the left side of the graph, illustrates a period of an external refresh command signal (CMD) as a function of temperature. As illustrated by G13, the period of the external refresh command signal decreases from a maximum of 3 seconds to a minimum of 80 ms as the temperature of the DRAM device increases. This decrease in the length of the refresh period must be sufficient to account for the higher leakage currents that are present at higher temperatures in order to maintain data reliability.
FIG. 2 is a block diagram of a conventional memory system, which includes a memory controller 14 and a high capacity DRAM device 10. The DRAM device 10 is illustrated as including a temperature sensor 12, which measures the temperature of the DRAM device 10. In particular, the temperature sensor 12 generates a temperature signal Tmp that is provided to the memory controller 14. In response, the memory controller 14 determines, based on a relationship such as shown by FIG. 1, the appropriate frequency of an external refresh command CMD provided to the DRAM device 10. In this manner, the memory controller 14 may control the timing of refresh operations performed within the DRAM device 10 in order to prevent data errors caused by storage capacitor leakage.